In today's rapidly advancing world of semiconductor manufacturing, integration levels are increasing, device features are becoming smaller and greater demands are being made for improved device performance. As CMOS, complementary metal oxide semiconductor, devices are scaled to smaller sizes for future technologies, new materials and concepts are necessary to meet the advanced performance requirements.
CMOS technology includes NMOS (N-type metal oxide semiconductor) and PMOS (P-type metal oxide semiconductor) devices formed on the same substrate and in the same die. A critical aspect of high performance in NMOS and PMOS and various other devices is device speed. For devices to operate at high speeds, it is necessary to have a very low resistance, including a very low contact resistance between metal interconnect structures and the NMOS and PMOS transistors. Contact is made to the gate electrodes of the respective transistors as well as to both the source and drain regions of the associated transistors. One approach to provide a low contact resistance is to utilize source/drain extension regions that are implanted with dopant impurities that reduce resistance. After dopant impurities are introduced, however, they are activated using high temperature activation processes and the thermal dopant activation processes are inefficient for the materials being used as channel materials in advanced technologies.